The present invention relates to a method of manufacturing a semiconductor device exhibiting reduced capacitance loading. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices comprising sub-micron dimensions and exhibiting high circuit speed.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as xe2x80x9cdamascenexe2x80x9d-type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or inter-layer dielectric (ILD) between vertically spaced metallization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical-mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that the contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require rapid speed semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in sub-micron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with sub-micron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyimide materials, when employed as inter-metal dielectric layers, cause moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization levels.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization level and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metallization level usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Electroless plating of Cu generally involves the controlled auto-catalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode (comprising the surface(s) to be plated) from an external source (i.e., a power supply) for reducing Cu ions in solution and depositing reduced Cu metal atoms on the plating surface(s). In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated herein. A physical vapor deposition technique, such as sputtering, is useful for depositing the nucleation/seed layer.
Another technique to increase the circuit speed is to reduce the capacitance of the inter-layer dielectrics. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit speed. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect RC at deep sub-micron regimes, e.g., less than about 0.18 micron.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an ILD ranges from about 4.0 for dense silicon dioxide to over 8.0 for deposited silicon nitride. The value of the dielectric constant expressed herein is based upon a value of one for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permittivity have been explored. The expression xe2x80x9clow-kxe2x80x9d material has evolved to characterize materials with a dielectric constant less than about 3.9.
One type of low-k material that has been explored is a group of flowable oxides, which are basically ceramic polymers, such as hydrogen silsesquioxane (HSQ). Such polymers and their use are disclosed in, for example, U.S. Pat. Nos. 4,756,977 and 5,981,354. HSQ-type flowable oxides have been considered for gap filling between metal lines because of their flowability and ability to fill small openings. HSQ-type flowable oxides have been found to be vulnerable to degradation during various fabrication steps, including plasma etching.
There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD. Organic low-k materials which offer promise are carbon-containing dielectric materials such as FLARE 20(trademark) dielectric, a poly(arylene) ether, available from Allied Signal, Advanced Micromechanic Materials, Sunnyvale, Calif.; BCB (divinylsiloxane bis-benzocyclobutene), and Silk(trademark) or porous Silk(trademark) dielectric, organic polymers, available from Dow Chemical Co., Midland, Mich.; and organic-doped silica glasses (OSG) (also known as carbon-doped glasses) including Black-Diamond(trademark) dielectric available from Applied Materials, Santa Clara, Calif., Aurora(trademark) dielectric available from ASM America, Inc., Phoenix, Ariz., and Coral(trademark) dielectric available from Novellus, San Jose, Calif.
In attempting to employ such carbon-containing low-k materials in interconnect technology, as for gap filling or as an ILD, it was found that their dielectric constant became undesirably elevated as a result of processing. For example, the dielectric constant of BCB was found to increase from about 2.6 to greater than about 4.
A problem associated with the use of many low-k dielectric materials is that these materials can be damaged by exposure to oxidizing or xe2x80x9cashingxe2x80x9d systems, which remove a resist mask used to form openings, such as vias, in the low-k dielectric material. This damage can cause the surface of the low-k dielectric material to become a water absorption site, if and when the damaged surface is exposed to moisture. Subsequent processing, such as annealing, can result in water vapor formation, which can interfere with subsequent filling, with a conductive material, of a via/opening or a damascene trench formed in the dielectric layer. For this reason, the upper surface of the low-k dielectric material is typically protected from damage during removal of the resist mask by a capping layer, such as silicon oxide, disposed over the upper surface. Silicon oxide capping layers, however, require an additional process step of forming the silicon oxide layer.
Antireflective coatings (ARC) are frequently employed to help provide sub-micron images during photomicrographic processing. The ARC cuts down on light scattering, which helps in the definition of small images, minimizes standing wave effects, and improves image contrast during photoresist exposure. However, the use of an ARC requires additional processing steps, including spin-on and baking steps. In addition ARC layers, along with capping layers, suffer from poor adhesion to the ILD surface.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip-chip/package assemblies, transistors, capacitors, microprocessors, and random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.
There exists a need for methodology enabling the use of low-k carbon-containing dielectric materials as an ILD in high-density, multi-level connection patterns. There exists a particular need for methodology enabling the use of such low-k materials with low-k capping and ARC layers to avoid degradation of the low-k ILD properties while providing sub-micron feature sizes with enhanced resolution.
These and other needs are met by embodiments of the present invention, which provide a method of forming a semiconductor device with a first dielectric film on a semiconductor substrate. The first dielectric film is formed by depositing a lower layer of an organic-doped silica glass on a semiconductor substrate. A middle layer comprising a mixture of the organic-doped silica glass and a gradually increasing concentration of SiC is deposited on the lower layer and an upper layer of SiC is deposited on the middle layer. SiC has a lower dielectric constant than prior art ARC layers such as SiON.
The earlier stated needs are also met by other embodiments of the instant invention that provide a semiconductor device comprising a first dielectric film formed on a semiconductor substrate. The first dielectric film comprises a lower layer comprising an organic-doped silica glass, a middle layer comprising a mixture of organic-doped silica glass and a gradually increasing concentration of SiC, and an upper layer comprising SiC.
This invention address the needs for an improved method of forming capping layers and ARC layers on low-k ILD layers for use in high-density, multi-level interconnection patterns. This invention improves adhesion of capping layers and ARC layers to low-k ILDs. The present invention enables the manufacturing of high reliability, small feature sized semiconductor devices.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.